The present invention relates to a semiconductor memory device, and more particularly, to a data input apparatus in a semiconductor memory device.
Semiconductor memory devices are being continuously improved in order to increase the degree of integration and improve the operation speed. In order to improve operation speed, a synchronous memory device that can be operated in synchronization with a clock provided externally from a memory chip has been proposed.
One such proposed synchronous memory device is a single data rate (SDR) synchronous memory device that is synchronized with a rising edge of the clock provided from the external of the memory device to input and output a single data over a single period. However, the SDR synchronous memory device is insufficient when a system requires high speed operation. As a result, a double data rate (DDR) synchronous memory device that is synchronized with the rising edge and falling edge of the clock allowing two data to be processed in a single clock period has been proposed.
FIG. 1 is a block view schematically showing blocks associated with a write operation of the conventional DDR synchronous memory device.
Referring to FIG. 1, the semiconductor memory device comprises: a data strobe buffer 10 receiving and buffering data strobe signals DQS and DQSB; a data strobe driver 12 driving a signal outputted from the data strobe buffer 10 to output a rising strobe pulse DQSRP and a falling strobe pulse DQSFP; a data input buffer 14 buffering data DQ inputted through a data input/output pad, a data delay unit 16 delaying an output signal of the data input buffer for a predetermined time and outputting an output signal; and a data alignment unit 18 latching input data DIN outputted from the data delay unit in synchronization with the data strobe signal to align them.
The rising data strobe pulse DQSRP is a signal synchronized with the rising edge of the data strobe signal DQS, and the falling data strobe pulse DQSFP is a signal synchronized with the falling edge of the data strobe signal DQS.
The delay unit 16 delays the buffered data by a predetermined time and allocates the input data DIN to the data alignment unit 18.
The data alignment unit 18 aligns the input data DIN by synchronizing the input data DIN with the rising data strobe pulse DQSRP and the falling data strobe pulse DQSFP. The data aligned by the data alignment unit 18 is transferred to a memory cell region via a global input/output line in response to a pulse applied from the external.
FIG. 2 is a timing diagram for explaining the operation of FIG. 1.
FIG. 2 confirms that the rising data strobe pulse DQSRP is synchronized with the rising edge of the data strobe signal DQS and the falling data strobe pulse DQSFP is synchronized with the falling edge of the data strobe signal DQS.
As FIG. 2 clearly shows, the data DIN inputted to the data alignment unit 18 is delayed through the delay unit 16 to secure a setup/hold time.
FIG. 3 shows a prior art method of turning-off the data strobe buffer upon entering into a test mode and aligning the data using the output of a clock buffer.
Referring to FIG. 3, the semiconductor device comprises a data strobe buffer 30, a data strobe driver 32, a data input buffer 34, a data delay unit 36, a data alignment unit 38, and a clock buffer 40.
The clock buffer 40 buffers an external clock signal pair CLK and CLKB that is inputted from outside to output an internal clock signal BCK.
The data strobe buffer 30 and the data strobe driver 32 have a similar configuration to the buffer 10 and the driver 12 as shown in FIG. 1; however, there is a difference, in that the data strobe buffer 30 and the data strobe driver 32 are operated in response to a test mode signal TM. That is, the data strobe buffer 30 and the data strobe driver 32 are turned-off upon entering into a test mode, in which the test mode signal TM is enabled.
When the test mode signal TM is enabled, the data strobe driver is synchronized with the internal clock signal BCK outputted from the clock buffer in order to output the data strobe pulse DQSRP and the falling data strobe pulse DQSFP. In other words, the rising data strobe pulse DQSRP is outputted in synchronization with the rising edge of the internal clock signal BCK, and the falling data strobe pulse DQSFP is outputted in synchronization with the falling edge of the internal clock signal BCK.
The data delay unit 36 and the data alignment unit 38 are operated identically to the data delay unit 16 and the data alignment unit 18 shown in FIG. 1; and therefore, a detailed description will be omitted.
However, in the prior art shown in FIG. 3, it is difficult to secure the data setup/hold time upon entering into the test mode, since the pulse signals DQSRP and DQSFP, which are used as the data alignment signal of the data alignment unit 38, are synchronized by means of the internal clock signal BCK as shown in FIG. 3. The reason is that the degree delayed by means of the delay unit 36 is determined based on the data strobe buffer 30, although a timing of the internal clock signal BCK, which is buffered by means of the clock buffer, is slower than that of the signal buffered by means of the data strobe buffer. In particular, the clock buffer 40 is distributed at the center of the chip, the data strobe buffer 30 and the data strobe driver 32 are distributed at the left of the chip, and the data block (DQ pad, data input buffer, data delay unit, data alignment unit) is distributed at the left-center of the chip. The output signal BCK of the clock buffer is input to the data block via the data strobe driver 32, and thus the moving path of the signals is long, and it takes much more time for the internal clock signal BCK to be input to the data block. Accordingly, it is more difficult to secure the data setup/hold time margins in the semiconductor device shown in FIG. 3.
FIG. 4 is a timing diagram for explaining the operation of FIG. 3. Referring to FIG. 4, the problems can be more obviously confirmed.
FIG. 4 confirms that when the semiconductor device shown in FIG. 3 is operated in a test mode, the setup/hold time window characteristics are different from that of the semiconductor memory device when it is operated normally. In FIG. 4, the test mode TM is enabled at a high level turning off the data strobe buffer 30 and the data strobe driver 32. The pulse signals DQSRP and DQSFP are synchronized with the rising edge and falling edge of the internal clock signal BLCK respectively. FIG. 4 shows that the pulse signals DQSRP and DQSFP are delayed more than the input data DIN (which is delayed by the data delay unit 36).
If the amount of delay delayed by the data delay unit 36 is increased so that the setup time conforms to the hold time when the semiconductor device is in the test mode, problems occur when the semiconductor device operates in a non-test mode (i.e., normal mode). In the normal mode, the data strobe buffer 30 and the data strobe driver 32 are operated normally; and therefore, the amount of delay cannot be increased based on the problems incurred when the semiconductor device is in the test mode.